The present invention relates to low power electrical circuits, and more particularly to low power memory decoders.
Complementary Metal-Oxide-Semiconductor (CMOS) is a technology for constructing Integrated Circuits (ICs). CMOS technologies are used in microprocessors, microcontrollers, Static Random Access Memory (SRAM), Application Specific Integrated Circuits (ASIC), and wide varieties of electrical circuits. The word “complementary” refer to the fact that the typical design style with CMOS uses complementary pairs of p-channel and n-channel metal-oxide-semiconductor Field Effect Transistors (FETs). Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not waste as much power as other forms of logic, such as Transistor-Transistor Logic (TTL) or N-channel Metal-Oxide-Semiconductor (NMOS) logic, that normally have significant standby leakage current even when not changing state. By definition, “standby leakage current” is the current flowing through the power supply of a circuit when the circuit is not changing state. The standby leakage currents of CMOS circuits are typically much lower than that of other types of circuits. It was primarily for this reason that CMOS became the most used technology to be implemented in integrated circuits.
As IC technologies advanced, the channel lengths of MOS transistors have been reduced. Currently, transistors with channel length as short as 5 nanometers (nm) have been manufactured. The standby leakage currents of CMOS circuits increase rapidly with decreasing channel lengths of CMOS transistors. For CMOS circuits using transistors with channel lengths longer than 200 nm, the standby leakage currents of the CMOS circuits are typically negligible. On the other hand, short channel CMOS circuits can waste significant power even when the circuit is not changing state. Consequently, it is often necessary to provide power saving methods to reduce standby leakage currents for short channel CMOS circuits.
Currently, most of power saving methods are controlled by logic circuits called power management units. A prior art Power Management Unit (PMU) monitors the activities of circuit blocks, and turns off the power supply of a circuit block that is not in use in order to save power. FIG. 1(a) is a flowchart showing typical operations of a prior art PMU, and FIG. 2(a) is a timing diagram showing the power supply voltages of a circuit block controlled by a prior art PMU. At normal operation conditions, the substrate terminals and the source terminals of the p-channel transistor that are connected to the power source are connected to a power line at voltage Vdd, and the n-channel substrate terminals and the source terminals of n-channel transistors that are connected to power source are connected to a ground line at voltage Vss; the power supply voltage (Vpower) is equal to (Vdd−Vss) and it is typically set at a standard voltage (Vstd). Each generation of CMOS technology is optimized for a particular standard voltage. For examples, the standard voltage for 180 nm technology is typically 1.8 volts, Vstd is typically 1.2 volts for 130 nm technology, Vstd is typically 1.0 volt for 90 nm technologies, and so on. The prior art PMU monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, it stays in full power, which means that Vpower applied on the circuit block stays at Vstd. If a circuit block is no longer needed to work, the PMU can shut down the circuit block to save power. For example, the PMU found that starting from time T1 in FIG. 2(a), a circuit block is no longer needed. Typically, a prior art PMU cannot turn off the power immediately at time T1. When the power supply of a circuit block is turned off, the data stored in the volatile memory devices inside the circuit block can be lost. When the power is turned back on, the circuit may not return to previous state because the contents in memory devices can be different after power up. Examples of volatile memory devices include Static Random Access Memory (SRAM), Content Addressable Memory (CAM), registers, latches, flip-flops, and so on. It is typically necessary to store the contents of volatile memory devices before shutting down the power. As shown in FIG. 1(a), when the PMU determines to shut down a circuit block to save power, it typically needs to store data in memory devices into nonvolatile memory before turning off the power of the circuit block to save power. As shown in FIG. 2(a), the circuit block is not in use since time T1, but the PMU need to maintain in full power on the circuit block until time T3. The storage time (T3-T1) is used to store contents in memory devices into nonvolatile memory devices such as hard discs. This procedure can be time consuming, and it can burn a lot of power. After time T3, the PMU can shut down the power, and Vpower gradually approaches zero, as shown in FIG. 2(a). During this period of time, the PMU continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in power saving mode, as shown in FIG. 1(a). If the circuit block is needed, the PMU restarts the circuit block by turning on its power at time T2, as shown in FIG. 2(a). However, the circuit block is not ready to function until the data are restored back to the memory devices in the circuit block at time T4, as shown in FIG. 2(a). This recovery time (T4-T2) can be long, and the circuit block can consume a lot of power during recovery. After time T4, the circuit block is ready to restart normal operations, as illustrated in FIG. 2(a).
The operation of prior art PMUs can be very complex, especially when a circuit block comprises many memory devices. The procedures to shut down and restore a circuit block can be time consuming, and the processes can consume a lot of power. The PMU itself also can consume significant power. It is therefore highly desirable to develop power saving modes that support fast recovery time.
In U.S. Pat. No. 7,782,655 and in U.S. Pat. No. 8,164,969, Shau disclosed “Hybrid Subthreshold (SubVt) Circuits” that solved many problems of prior art power management units. FIG. 1(b) is a flowchart showing typical operations of a prior art Hybrid SubVt circuit. FIG. 2(b) is a timing diagram showing the voltages applied on a circuit block controlled by a prior art Hybrid SubVt controller, where NVps is the power connection to the source terminals of p-channel MOS transistors that are connected to power source, NVpb is the electrical connection to the substrate terminals of p-channel MOS transistors, NVns is the ground connection to the source terminals of n-channel MOS transistors that are connected to power source, and NVnb is the electrical connection to the substrate terminals of n-channel MOS transistors. At normal operation, Hybrid SubVt circuits operates in the same condition as typical CMOS circuits, where NVpb is connected to NVps at power supply voltage Vdd, NVnb is connected to NVns at ground voltage Vss, and the power supply voltage (Vpower) equals standard voltage (Vstd), as shown in the timing diagram in FIG. 2(b). A Hybrid SubVt controller monitors the activities of the whole circuit to determine whether a particular circuit block needs to work or not. If the circuit block needs to work, then it stays in full power, which means that Vpower of the circuit block stays at Vstd. If a circuit block is no longer needed to work, the circuit can be placed into subthreshold power saving mode, as shown in FIG. 1(b). At subthreshold power saving mode, the power supply voltage (Vpower) is reduced to a level that is lower than the threshold voltages (Vt) of the MOS transistors in the circuit block. Under SubVt mode, the standby leakage current of the circuit can be reduced by 99% or more relative to the standby leakage current of the same electrical circuit under normal operation mode, while all the memory devices still can hold their data. It is therefore possible to get into SubVt power saving mode immediately without the need to store the data in memory devices into nonvolatile memory devices. For example, the controller found that starting from time T1 in FIG. 2(a) the circuit block is no longer needed. Right after T1, the circuit can get into SubVt power saving mode, where NVpb is pulled up to a voltage Vpb that is higher than Vdd, NVnb is pulled down to a voltage Vns that is lower than Vss, the voltage on NVps is allowed to drop no lower than a voltage Vpt, and the voltage on Vns is allowed to rise no higher than a voltage Vnt, as shown in FIG. 2(b). The voltage difference (Vpt−Vnt) is controlled to be lower than Vt, so that the circuit block is under SubVt mode. During this period of time, the controller continues to monitor the activities of the whole circuit to determine whether the circuit in power saving mode is needed or not. If the circuit block is not needed, it can stay in SubVt mode, as shown in FIG. 1(b). If the circuit block is needed, the controller restarts the circuit block by going back to normal operation mode at time T2, as shown in FIG. 2(b). Since there is no need to restore data from nonvolatile memory devices, the circuit block can go back to normal operation mode instantly after time T2, as shown in FIG. 2(b).
Shau's hybrid SubVt circuits significantly reduced the wastes in power during storage time and recovery time. However, hybrid SubVt mode is applicable typically when the circuit block does not need to do any work. It is highly desirable to develop a power saving mode that is applicable on circuit blocks that need to do work.
MOS transistors with channel length longer than 25 nm are typically planar transistors. FIG. 8(a) is a simplified cross-section diagram illustrating the structures of a planar MOS transistor. The gate of this planar transistor is formed between a gate insulator (805) and a semiconductor substrate (804) on a planar surface. Ideally, the electrical current between the drain terminal (803) and the source terminal (802) is controlled by the voltage on the gate terminal (801). For short channel transistors, it is well known that drain voltage coupled to the semiconductor substrate can induced leakage in substrate areas that are away from the gate area. One solution to solve this Drain Voltage Induced Leakage (DVIL) problem is to manufacture transistors in a thin semiconductor body that is controlled by gates from multiple sides. A multiple-gate MOS transistor, by definition, is an MOS transistor that comprises gates on multiple sides of a semiconductor substrate. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. Current art MOS transistors with channel length shorter than 25 nm are typically multiple-gate transistors.
FIG. 8(b) is a simplified diagram illustrating the three dimensional structures of one example of a multiple-gate MOS transistor known as “FinFET”. The distinguishing structure of a FinFET is a thin slice of semiconductor “fin” (814) that forms the body of the device. This semiconductor fin (814) is formed above field oxide so that a gate electrode (810) can wraps around three surfaces of the fin (814), as shown in FIGS. 8(b, c). The source (817) and drain (818) terminals of the FinFET are formed by heavily doped diffusion regions on the fin, as shown in FIG. 8(b). FIG. 8(c) is a simplified cross-section diagram illustrating the gate structures of the FinFET in FIG. 8(b). The interfaces between the gate electrode (810) and the semiconductor fin (814) on the two side surfaces (811, 812) of the fin form the gate interfaces of the FinFET. The top surface of the semiconductor body (814) of the transistor is typically separated from the gate electrode (810) by a thick insulator (819) so that the top surface is not active. This Wrap-around gate structure provides a better electrical control over the channel and thus helps in overcoming short-channel effects.
Similar Multiple-gate MOS transistors have been manufactured. FIG. 8(d) is a simplified cross-section diagram illustrating the gate structures of one example of a multiple-gate MOS transistor known as “TriFET”. A gate electrode (820) wraps around three surfaces of a thin slice of semiconductor body (824), as shown in FIG. 8(d), while all three interfaces (821-823) between the gate electrode (820) and the semiconductor body (824) form the gates of the TriFET. The cross-section of the semiconductor fin does not have to be a rectangle. FIG. 8(e) is a simplified cross-section diagram illustrating the gate structures of another TriFET that has a semiconductor body (834) that is narrower on top and wider on bottom. FIG. 8(f) is a simplified cross-section diagram illustrating the gate structures of one example of a multiple-gate MOS transistor known as “Omega FET”. The “Omega FET” design is named after the similarity between the Greek letter omega (Ω) and the shape in which the gate electrode (840) wraps around its semiconductor body (844), as shown in FIG. 8(f). FIG. 8(g) is a simplified cross-section diagram illustrating the gate structures of one example of a multiple-gate MOS transistor known as “Gate-all-around (GAA) FET”. The gate electrode (850) of a GAA FET surrounds a semiconductor body (854) on all sides, as shown in FIG. 8(g). The body (854) of a GAA FET does not have to be rectangle; it can be a circle or other shapes. These and other types of multiple-gate MOS transistors achieve better power efficiency by reducing short channel effects. It is desirable to build hybrid circuits using multiple-gate MOS transistors to achieve further power efficiency. With reference to previous patent application (Ser. No. 15/094,960), this application provides additional considerations on implementations of hybrid circuits using multiple-gate transistors.
The major difference between hybrid circuits that use planar MOS transistors versus hybrid circuits that use multiple-gate MOS transistors is that the latter may or may not have effective substrate connections that can connect to the substrate terminals of many multiple-gate MOS transistors. FIG. 9(a) is a simplified cross-section diagram illustrating substrate connections for multiple-gate MOS transistors. In this example, the semiconductor bodies (NFn0, NFn1) of two n-channel multiple-gate MOS transistors (Mgn0, Mgn1) are connected together through the p-type well (PWell) under those transistors; a semiconductor contact (Cpw) penetrating through field oxide (OXf) provides electrical connection from a metal line (NVpw) to PWell; heavily doped p-type diffusion area (PWdp) is deposited in the PWell to reduce the resistance of this substrate connection, as shown in FIG. 9(a). In this example, PWell is completely surrounded by NWell so that it is isolated from the p-type substrate (Psub) of the bulk semiconductor. However, it is also possible to allow PWell to be connected to Psub. Similarly, the semiconductor bodies (NFp0, NFp1) of two p-channel multiple-gate MOS transistors (Mgp0, Mgp1) are connected together through the n-type well (NWell) under those transistors; a semiconductor contact (Cnw) penetrating through field oxide (OXf) provides electrical connection from metal line (NVnw) to NWell; heavily doped n-type diffusion area (NWdp) is deposited in the NWell to reduce the resistance of this substrate connection, as shown in FIG. 9(a). FIG. 9(d) is a simplified symbolic diagram illustrating the equivalent circuit of the n-channel multiple-gate MOS transistors (Mgn0, Mgn1) in FIG. 9(a). The substrate terminal (NVnb) of the transistor is connected to PWell connection (NVpw) through an electrical path that is represented by a resistor (Rpw) in FIG. 9(d). The substrate terminal (NVnb) is coupled to the source terminal (NVns) through a junction diode (DSn), and it is also coupled to the drain terminal (NVnd) through another junction diode (DDn). The gate terminal (NVng) controls the gate voltage. During switching events, a substrate current (Ibn) may be generated through impact ionization or recombination mechanisms. When the substrate current (Ibn) flow toward NVpw through Rpw, the IR drop may cause a voltage difference between the substrate voltage (Vnb) at NVnb and the well voltage (Vpw) at NVpw. This voltage difference is typically small, so that the PWell connection in FIG. 9(a) is typically an effective electrical substrate connection to the substrate terminals of both n-channel multiple-gate transistors (Mgn0, Mgn1). FIG. 9(e) is a simplified symbolic diagram illustrating the equivalent circuit of the p-channel multiple-gate MOS transistors (Mgp0, Mgp1) in FIG. 9(a). The substrate terminal (NVpb) of the transistor is connected to NWell connection (NVnw) through a conducting path that is represented by a resistor (Rnw) in FIG. 9(e). The substrate terminal (NVpb) is coupled to the source terminal (NVps) through a junction diode (DSp), and it is also coupled to the drain terminal (NVpd) through another junction diode (DDp). The gate terminal (NVpg) controls the gate voltage. During switching events, a substrate current (Ibp) may be generated through impact ionization or recombination mechanism. When the substrate current (Ibp) flow toward NVnw through Rnw, the IR drop may cause a voltage difference between the substrate voltage (Vpb) at NVpb and the well voltage (Vnw) at NVnw. This voltage difference is typically very small, so that the NWell connection in FIG. 9(a) is typically an effective electrical substrate connection to the substrate terminals of both p-channel multiple-gate transistors (Mgp0, Mgp1). For hybrid circuits that comprise multiple-gate MOS transistors with effective substrate connections such as the example shown in FIG. 9(a), they can be controlled in similar ways as planar MOS transistors to support SupVt or SubVt hybrid circuits. The methods, embodiments, and examples disclosed in patent application Ser. No. 15/094,960, U.S. Pat. No. 7,782,655, or U.S. Pat. No. 8,164,969 are all applicable to such cases.
FIG. 9(b) is a simplified cross-section diagram of a circuit that has identical electrical connections to the wells (Pwell, Nwell) as those shown in FIG. 9(a). In this example, the semiconductor bodies (NFn2, NFn3) of n-channel multiple-gate MOS transistors (Mgn2, Mgn3) are isolated from PWell by field oxide (OXf), and the semiconductor bodies (NFp2, NFp3) of p-channel multiple-gate MOS transistors (Mgp2, Mgp3) are also isolated from NWell by field oxide (OXf), as shown in FIG. 9(b). In this example, the well connections (NVpw, NVnw) can only influence the substrates (NFn2, NFn3, NFp2, NFp3) of those multiple-gate transistors (Mgn2, Mgn3, Mgp2, Mgp3) through capacitor coupling of the capacitor formed across filed oxide (OXf). FIG. 9(f) is a simplified symbolic diagram illustrating the equivalent circuit of the n-channel multiple-gate MOS transistors (Mgn2, Mgn3) in FIG. 9(b). This equivalent circuit is identical to the equivalent circuit in FIG. 9(d) except that the substrate terminal (NVnb) is coupled to PWell connection (NVpw) by a capacitor (Coxf) instead of a resistor (Rpw). Since this capacitor (Coxf) is formed across the field oxide (OXf), the capacitor is very small. The influence of the voltage on well connection (NVpw) from substrate terminal (NVnb) is very small. The substrate current (Ibn) mostly flow through the junction diode (DSn) to the source terminal (NVns). Therefore, the substrate voltage (Vnb) on the substrate terminal (NVnb) can be significantly different from the voltage on the well connection (NVpw). FIG. 9(g) is a simplified symbolic diagram illustrating the equivalent circuit of the p-channel multiple-gate MOS transistors (Mgp2, Mgp3) in FIG. 9(b). This equivalent circuit is identical to the equivalent circuit in FIG. 9(e) except that the substrate terminal (NVpb) is coupled to NWell connection (NVnw) by a capacitor (Coxf) instead of a resistor (Rnw). The substrate voltage (Vpb) on the substrate terminal (NVpb) can be significantly different from the voltage on the well connection (NVnw). For the example shown in FIG. 9(b), the well connections (NVpw, NVnw) do not provide effective substrate connections to the multiple-gate transistors (Mgn2, Mgn3, Mgp2, Mgp3). For hybrid circuits that comprise multiple-gate MOS transistors with isolated substrate connections such as the example shown in FIG. 9(b), the substrate voltages of MOS transistors are not necessarily the same as the voltages on wells. The methods, embodiments, and examples disclosed in patent application Ser. No. 15/094,960, U.S. Pat. No. 7,782,655, or U.S. Pat. No. 8,164,969 are still applicable to such cases except that the substrates terminals of transistors can have different voltages.
FIG. 9(c) is a simplified cross-section diagram of a circuit that has identical electrical connections to the wells (Pwell, Nwell) as those shown in FIG. 9(a). In this example, the semiconductor bodies (NFn4, NFn5) of n-channel gate-all-around MOS transistors (Mgn4, Mgn5) are not only isolated from PWell by field oxide (OXf) but also shielded from well voltage by the gate electrodes. The semiconductor bodies (NFp4, NFp5) of p-channel gate-all-around MOS transistors (Mgp4, Mgp5) are not only isolated from NWell by field oxide (OXf), but also shielded from well voltage by the gate electrodes, as shown in FIG. 9(c). In this example, the well connections (NVpw, NVnw) are completely disconnected from the substrates (NFn4, NFn5, NFp4, NFp5) of those multiple-gate transistors (Mgn4, Mgn5, Mgp4, Mgp5). FIG. 9(h) is a simplified symbolic diagram illustrating the equivalent circuit of the n-channel multiple-gate MOS transistors (Mgn4, Mgn5) in FIG. 9(c). This equivalent circuit is identical to the equivalent circuit in FIG. 9(d) except that the substrate terminal (NVnb) is disconnection from PWell connection (NVpw). The substrate voltage (Vnb) on the substrate terminal (NVnb) is not influenced by the voltage on the well connection. FIG. 9(i) is a simplified symbolic diagram illustrating the equivalent circuit of the p-channel multiple-gate MOS transistors (Mgp4, Mgp5) in FIG. 9(c). This equivalent circuit is identical to the equivalent circuit in FIG. 9(e) except that the substrate terminal (NVpb) is disconnected from NWell connection. The substrate voltage (Vpb) on the substrate terminal (NVpb) is not influenced by the voltage on the well connection (NVnw). For the example shown in FIG. 9(c), the well connections (NVpw, NVnw) do not provide effective substrate connections to the multiple-gate transistors (Mgn4, Mgn5, Mgp4, Mgp5). For hybrid circuits that comprise multiple-gate MOS transistors with isolated substrate connections such as the example shown in FIG. 9(c), the substrate voltages of MOS transistors are not necessarily the same as the voltages on wells. The methods, embodiments, and examples disclosed in patent application Ser. No. 15/094,960, U.S. Pat. No. 7,782,655, or U.S. Pat. No. 8,164,969 are still applicable to such cases except that the substrates terminals of transistors can be isolated.
Multiple-gate MOS transistors may or may not have electrical connections to the wells in the bulk semiconductor substrate, as shown by the examples in FIGS. 9(a-i). All multiple-gate MOS transistors still are 4 terminal devices. Each multiple-gate MOS transistor has a substrate terminal, and the voltage on the substrate terminal can influence operations of the transistor. The substrate terminal of a multiple-gate MOS transistor needs to provide a path for substrate current generated by impact ionization or recombination mechanisms. When a substrate terminal is connected to an effective substrate connection, such as the examples shown in FIGS. 9(a, d, e), the influence of substrate current can be small. When a substrate terminal is floating, such as the examples shown in FIGS. 9(b, c, f-i), the transistor is less stable. The voltage on the substrate terminal of a multiple-gate MOS transistor can influence the channel current of the transistor. FIG. 9(j) shows a symbolic equivalent circuit for the effective gate voltage (VGe) of a transistor. The voltage on the gate terminal (VG) couples to VGe through a gate capacitor (Cg), the voltage on the drain terminal (VD) couples to VGe through a drain capacitor (Cd), the voltage (VS) on the source terminal couples to VGe through a source capacitor (Cs), and the voltage (VB) on the substrate terminal couples to VGe through a substrate capacitor (Cb). Capacitors Cg, Cd, Cs, Cb are simplified equivalent circuits representing complex three dimensional effects. Ideally, Cg should be much larger than Cs, Cd, and Cb so that the effective gate voltage (VGe) equals the gate voltage (VG). In reality, Cd, Cb, and Cs can cause none-ideal effects on the operations of MOS transistors. The well-known example is the drain voltage induced leakage current caused by coupling voltage from VD through Cd. Relative to planar transistors, multiple-gate transistors effectively reduced Cd and Cs, which reduced the drain current induced leakage. By ignoring Cs and Cd, the equivalent circuit in FIG. 9(j) can be simplified into the simplified symbolic equivalent circuit in FIG. 9(k). From FIG. 9(k), the effective gate voltage VGe can be determined as VGe=VG*[Cg/(Cg+Cb)]+VB*Cb/[(Cg+Cb)]. The influence of VB on the effective gate voltage is called “body effect”. When Cg is much larger than Cb, body effect is negligible. When Cb is not negligible comparing to Cg, reversed bias substrate voltage VB can reduce channel current. To turn off a transistor, body effect is desirable because it helps to reduce leakage current. To turn on a transistor, body effect is typically not desirable because it can reduce channel current. Cb is a function of doping profiles in the substrate, and a function of voltages. It is desirable to control the doping profile of a transistor so that Cb is much smaller than Cg when the transistor is turned on, and Cb is large enough to cause body effect when the transistor is turned off. For such ideal transistors, it is desirable to set substrate voltage in reverse bias because that helps in reducing leakage while the influence in speed is small.
When the substrate terminals of multiple gate transistors are connected to effective substrate connections, such as the examples shown in FIGS. 9(a, d, e), the substrate voltages can be controlled to help power savings. When the substrate terminals are floating, such as the examples shown in FIGS. 9(b, c, f-i), hybrid power saving modes still can be implemented by controlling the source and drain voltages without controlling substrate voltages.
This application is a continuation-in-part application of previous patent application with a Ser. No. 15/210,465, with a title “Low Power High Performance Electrical Circuits”, and filed by the applicant of this invention on Jul. 3, 2016. The patent application discloses power saving mode related to memory decoders.